SV13. SystemVerilog Casting Guide
Casting in SystemVerilog is a powerful mechanism for explicitly converting data between different types, sizes, and sign interpretations. This guide covers t...
Posts by Tag
- Arithmetic 3
- Data Type 2
- Net 2
- Procedural Statements 2
- Levels of Abstraction 1
- Design Process 1
- simulation 1
- synthesis 1
- elaboration 1
- ASIC 1
- FPGA 1
- event scheduling 1
- delta cycles 1
- non-blocking assignments 1
- Bugs 1
- X-value 1
- Variable 1
- Array 1
- Package 1
Arithmetic
SV12. Difference between Bitwise NOT (~) and Logical NOT (!)
When working with Verilog or SystemVerilog, itβs crucial to understand the distinction between the bitwise NOT operator (~) and the logical NOT operator (!)....
SV11. Signed Arithmetic in SystemVerilog
This page summarizes the key rules and pitfalls for synthesizable signed arithmetic in SystemVerilog, focusing on vector size, signed vs. unsigned behavior, ...
Data Type
SV8. SystemVerilog Implicit Net Declaration
Tired of silent bugs caused by undeclared signals in SystemVerilog? This article explains how implicit net declarations work, when they happen, and how to av...
SV7. SystemVerilog Built-in Data types: Data Type and Types
It covers the key distinctions between: Nets (representing connections) and Variables (representing storage). 2-state and 4-state data types, and how they re...
Net
SV8. SystemVerilog Implicit Net Declaration
Tired of silent bugs caused by undeclared signals in SystemVerilog? This article explains how implicit net declarations work, when they happen, and how to av...
SV7. SystemVerilog Built-in Data types: Data Type and Types
It covers the key distinctions between: Nets (representing connections) and Variables (representing storage). 2-state and 4-state data types, and how they re...
Procedural Statements
SV15. SystemVerilog Clock-to-Q Modeling: Why Non-Blocking Assignments Matter
This guide focuses on one of the most important timing parameters: Clock-to-Q delay and how to model it effectively in RTL design.
SV14. Unique and Priority Identifiers in SystemVerilog
SystemVerilog provides three special keywords (unique, unique0, and priority) that can be used with case and if statements to provide synthesis tools with op...
Levels of Abstraction
SV1. Levels of Abstraction in Digital Circuit Design
Understanding different levels of abstraction is crucial for effective digital circuit design. Learn about algorithmic, RTL, gate, and switch levels in Syste...
Design Process
SV2. Comparing FPGA and ASIC Design Processes
Learn the key differences between FPGA and ASIC design flows. Understand when to choose each approach and the trade-offs involved in hardware design decisions.
simulation
SV3. Simulation and Synthesis in Digital Design
Explore the fundamental differences between simulation and synthesis in digital design. Understand how your SystemVerilog code behaves in simulation versus h...
synthesis
SV3. Simulation and Synthesis in Digital Design
Explore the fundamental differences between simulation and synthesis in digital design. Understand how your SystemVerilog code behaves in simulation versus h...
elaboration
SV3. Simulation and Synthesis in Digital Design
Explore the fundamental differences between simulation and synthesis in digital design. Understand how your SystemVerilog code behaves in simulation versus h...
ASIC
SV4. Differences between ASIC and FPGA RTL Coding
Master the key differences in RTL coding styles for ASIC and FPGA targets. Learn about timing considerations, resource constraints, and optimization strategi...
FPGA
SV4. Differences between ASIC and FPGA RTL Coding
Master the key differences in RTL coding styles for ASIC and FPGA targets. Learn about timing considerations, resource constraints, and optimization strategi...
event scheduling
SV5. Simulation Event Scheduling in Verilog/SystemVerilog
Deep dive into simulation event scheduling, delta cycles, and non-blocking assignments. Understand how Verilog simulators handle timing and event ordering in...
delta cycles
SV5. Simulation Event Scheduling in Verilog/SystemVerilog
Deep dive into simulation event scheduling, delta cycles, and non-blocking assignments. Understand how Verilog simulators handle timing and event ordering in...
non-blocking assignments
SV5. Simulation Event Scheduling in Verilog/SystemVerilog
Deep dive into simulation event scheduling, delta cycles, and non-blocking assignments. Understand how Verilog simulators handle timing and event ordering in...
Bugs
SV6. X Value Bugs in Digital Circuit Design (FPGA/ASIC)
π« can represent an uninitialized state, uncertainty, or a conflict in multiple driver situations. The X value does not physically exist in real hardware. π¦πΆπΊ...
X-value
SV6. X Value Bugs in Digital Circuit Design (FPGA/ASIC)
π« can represent an uninitialized state, uncertainty, or a conflict in multiple driver situations. The X value does not physically exist in real hardware. π¦πΆπΊ...
Variable
SV7. SystemVerilog Built-in Data types: Data Type and Types
It covers the key distinctions between: Nets (representing connections) and Variables (representing storage). 2-state and 4-state data types, and how they re...
Array
SV9. SystemVerilog Packed vs. Unpacked arrays
Ever wondered how packed vs. unpacked arrays really work in SystemVerilog? This article dives into the syntax, memory layout, and use cases of both - with pr...
Package
SV10. User-Defined Packages in SystemVerilog
If you work with SystemVerilog, you know the headaches that can come from improper scope management. In this wiki, I cover: β’ Why you should avoid $unit scop...