Learn FPGA Development
A curated reference of free AMD training, videos, and documents for learning FPGA and adaptive SoC design with Vivado and Vitis, plus a short list of community resources.
The Complete Guide to Hardware Pipeline Design with Backpressure
How to build a pipelined datapath with a ready/valid handshake that propagates backpressure automatically: the control signals, how to derive them, and synthesizable SystemVerilog and VHDL for a reusable pipeline stage.
Use VS Code for RTL Design with Vivado: A Practical End-to-End Workflow
In this post, I walk through a complete setup for mixed-language FPGA development (VHDL, Verilog, and SystemVerilog), including real-time syntax checks, symbol navigation, simulation, and Vivado project creation from Tcl.
SV19. Run C Code on a Custom RISC-V CPU: Fibonacci from Compiler to FPGA
Learn the full practical flow to run C code on a custom RISC-V SoC by compiling and executing a Fibonacci program from simulation to real FPGA hardware.
SV18. A Deep Dive into OBI: Building Your First Master and Slave Controllers
In this tutorial, we'll demystify OBI by designing and verifying a minimal master from the ground up.