AICLAB

The Complete Guide to Hardware Pipeline Design with Backpressure

How to build a pipelined datapath with a ready/valid handshake that propagates backpressure automatically: the control signals, how to derive them, and synthesizable SystemVerilog and VHDL for a reusable pipeline stage.

ASIC FPGA

Use VS Code for RTL Design with Vivado: A Practical End-to-End Workflow

In this post, I walk through a complete setup for mixed-language FPGA development (VHDL, Verilog, and SystemVerilog), including real-time syntax checks, symbol navigation, simulation, and Vivado project creation from Tcl.

ASIC FPGA

SV19. Run C Code on a Custom RISC-V CPU: Fibonacci from Compiler to FPGA

Learn the full practical flow to run C code on a custom RISC-V SoC by compiling and executing a Fibonacci program from simulation to real FPGA hardware.

RISC-V FPGA C

SV18. A Deep Dive into OBI: Building Your First Master and Slave Controllers

In this tutorial, we'll demystify OBI by designing and verifying a minimal master from the ground up.

OBI

SV17. FIFO Design and Implementation

A First-In-First-Out (FIFO) buffer is a fundamental digital design component that stores data in a queue-like structure. This guide provides a comprehensive explanation of FIFO design principles, depth calculation methods, and a complete SystemVerilog implementation suitable for synthesis.

FIFO

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